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Friday, May 13 • 4:30pm - 6:00pm
The CPU Cache: Instruction Re-Ordering Made Obvious

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The CPU cache has been described as one of the greatest inventions in the history of computer science. In the era of the modern multi-core CPU, software design increasingly relies upon the CPU cache to enable performance, and to forgive our software implementation transgressions. This performance comes at a cost: To make best use of underlying CPU resources, the CPU and compiler will conspire to re-order the instructions specified in our source code algorithms -- at compile-time, and at run-time. This re-ordering can be perplexing to new programmers, and confusing when debugging real-world scenarios. However, re-ordering is explicitly allowed by the C++ Standard under the “As-If” rule, with C++11 providing the programmer additional tools through language and library features such as the C++11 memory model, atomics, memory fences, and threading libraries.

This is a, “First Principles” (i.e., “introductory”) discussion of the CPU cache, its anatomy, and its ever-growing role in hardware and software design. Modern performant systems are implemented with explicit knowledge of the CPU cache’s structure and behavior. Discussion is made of CPU registers, CPU cache levels, the cache line, the data bus, the CPU instruction pipeline, the compiler’s duty, and the tremendous hijinks performed by execution units within the processor core at runtime which leads to instruction re-ordering -- for which the knowledgeable C++ programmer is grateful.

No programmer can be an expert on everything. However, increasingly most C and C++ programmers need to be conversant with CPU cache issues and terminology at this level, and such understanding will make compiler and runtime behavior (and especially instruction re-ordering) much more obvious. From here, one begins to think about how to leverage parallelism and be concerned with concurrency.

Speakers
avatar for Charles Bay

Charles Bay

Senior Software Engineer, F5 Networks
Software developer with 25+ years experience in large-scale and distributed systems in performance-sensitive environments including real-time processing, performance visualization, embedded systems, time-sensitive processing of large data sets, hardware status-and-control, and instrument/process/sub-assembly monitoring.



Friday May 13, 2016 4:30pm - 6:00pm
Booz Allen Hamilton

Attendees (34)